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EM MICROELECTRONIC-MARIN SA
EM6124
Digitally Programmable 8 to 25 Multiplex LCD Controller & Driver
Features
Slim IC for chip-on-board, with gold bumps for
Applications

Chip-On-Glas and Chip-On-Flex technologies Very simple 2-wire interface Digitally programmable multiplex rates: 8 x 113, 9 x 112, 16 x 105, 17 x 104, 20 x 101, 21 x 100, 24 x 97, 25 x 96 No lost pads while row driver from 8 up to 25 On chip: Voltage multiplier,VLCD up to 7 V (3 to 6 V at 25 C), 64 VLCD digitally programming steps, 4 VLCD temperature compensation factors, bias generation, VON / VOFF generation, frame frequency, display refresh RAM No busy state High noise immunity in inputs No external components needed, except a VLCD capacitor Digitally reversing row data Digitally reversing column data Inverting data function Blank function Set function Checker and Inverted Checker functions Sleep modes Low LCD operating current consumption Wide VDD voltage supply range, 2 to 5 V Wide temperature range: -40 to + 85 C Direct display of RAM data through the display data RAM
Mobile phones (GSM, DECT) Smart cards Automotive displays Portable, battery operated products Balances and scales, utility meters
Typical Operating Configuration
EM6124
Fig. 1
Pad Assignment
(To cascade ICs, please see Fig. 19 and contact EM-Marin.)
Description
The EM6124 is a low power CMOS LCD controller and driver. The 8, 16, 20 and 24 way multiplex are digitally programmable by the command byte. One additional line can be added for Icons or Inverted Video by programming 9, 17, 21 or 25 way multiplex. The display refresh is handled on chip by an internal RC oscillator via one selectable 25 x 116 RAM which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 25 x 116 bit RAM (a set bit corresponds to an activated LCD pixel). The EM6124 has very low dynamic current consumption, typically 70 A at VDD = 2 V, VLCD = 7 V making it particularly attractive for portable and battery powered products. The wide operating range on supply voltages and temperature offers much application flexibility. The LCD voltage, bias generation and frame frequency are generated on chip. The clock signal can be used to shift and to latch the data into the RAM.
(To contact Power Supplies, please see Fig. 20.)
EM6124
Fig. 2 www..com
1
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EM6124
Absolute Maximum Ratings
Parameter
Supply voltage range Supply high voltage range Internal generated VLCD Voltage at DI, DO, CLK, FR, RES Voltage at S1 to S121 Storage temperature range Electrostatic discharge max. to MIL-STD-883C method 3015 Maximum soldering conditions
Handling Procedures
Conditions
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Symbol
VDD1,2 VHV VLCD VLOGIC VDISP TSTO VSmax TSmax
-0.3 V to 6 V -0.3 V to 6 V 7V -0.3 V to VDD +0.3 V -0.3 V to VLCD +0.3 V -65 to +150 C 1000 V 250 C x 10 s
Operating Conditions
Parameter
Operating temperature Logic supply voltage Supply high voltage
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Symbol Min. Typ. Max. Unit
TA VDD1,2 VHV -40 2 2.5 3 3 +85 5.5 5.5 C V V
Table 2
Electrical Characteristics
VDD1 = VDD2 = 3 V, VHV = 2.5 to 5 V, and TA = -40 to +85 C, unless otherwise specified
Parameter
Standby supply current Standby supply current Dynamic supply current Standby supply current Sleep mode supply current Sleep mode supply current Control Signals DI, CLK, FR, RES1,RES2 Input leakage Input capacitance Low level input voltage High level input voltage DC output component VLCD (internally generated) VLCD
1) 2)
Symbol Test Conditions
IDD IHV IDD IHV IDD IHV See note See note1), VLCD step 30 (hexa) See note 2) See note 3), VLCD step 00 (hexa)
1)
Min.
Typ.
16 65 57 35 0.1 0.1
Max.
22 170 75 140
Units
A A A A A A
IIN CIN VIL VIH VDC VLCD VLCD VLCD step
VDD1,2 or VSS at TA = 25 C
-1 8 0 0.7 VDD1,2
1 0.3 VDD1,2 VDD1,2 100
See table 4 See note 4) See note 5)
30 6.15 3.15 - 7.09 62.5
A pF V V mV V mV
All outputs open, DI and CLK at VSS, mux ratio = 24, checker pattern. All outputs open, DI at VSS, fCLK = 1 MHz, mux ratio = 24, checker pattern. 3) DI and CLK at VSS, checker pattern, mux ratio = 8. 4) Initialization bits 18 to 23 = 110000 and initialization bits 10, 11 = 00; laser trimming on request. 5) Initialization bits 18 to 23 = 000000/111111.
Table 3
DC Output Component
Output
Row Driver Column Driver *VX =
Frame
n n+1 n n+1
Logic Data
0L 0L 0L 0L
Measured*
| VLCD - V1| | V4 - VSS | | VLCD - V2 | | V3 - VSS |
Guaranteed
V1 = 0.83 x VLCD 100 mV V2 = 0.66 x VLCD 100 mV V3 = 0.34 x VLCD 100 mV V4 = 0.17 x VLCD 100 mV
VX ( load = +1 A) + VX (load = -1 A) , mux 24 or 25 programmed, VLCD = 6 V, TA = 25 C. 2
Table 4
Test is performed for multiplex rate = 25. All multiplex rate 25 are guaranteed by design. If multiplex rate 25, test will be performed on request.
2
EM6124
Timing Characteristics
VDD1 = VDD2 = 2 to 3 V, VHV = 2.5 to 5 V, and TA = -40 C to +85 C
Parameter
Clock high pulse width Clock low pulse width Clock period Reset 1 pulse width Reset 2 pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time FR (internal frame frequency)
1)
Symbol Test Conditions
tCH tCL tper tRES1 tRES2 tCR tCF tDS tDH fFR1)
Min.
70 110 550 10 130
Typ.
Max.
Units
ns ns ns s ns ns ns ns ns Hz
200 200 20 260 75
EM6124 (n), FR = n times the desired LCD refresh rate where n is the EM6124 mux mode number; laser trimming on request. See Fig. 17.01 and 17.02 for more details concerning the frame frequency
Table 5a
VDD1 = VDD2 = 3 to 5 V, VHV = 2.5 to 5 V, and TA = -40 C to +85 C
Parameter
Clock high pulse width Clock low pulse width Clock period Reset 1 pulse width Reset 2 pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time FR (internal frame frequency)
1)
Symbol Test Conditions
tCH tCL tper tRES1 tRES2 tCR tCF tDS tDH fFR1)
Min.
50 55 350 10 80
Typ.
Max.
Units
ns ns ns s ns ns ns ns ns Hz
200 200 20 140 75
EM6124 (n), FR = n times the desired LCD refresh rate where n is the EM6124 mux mode number; laser trimming on request.
Table 5b
Timing Waveforms
Fig. 3
3
EM6124
1 Bit Interface Description
This 1 bit interface is very simple to use. There are three modes to load data into the EM6124.
Init.bit 8-9: Mux mode bits. The multiplex ratio is selected by these two bits. Table 8 shows the corresponding values. Init.bit 10-11: VLCD temperature coefficient is selected by these two bits. Table 11 shows the corresponding values. Init.bit 12: Checker bit gives the possibility to force all outputs segments in checked form (see Fig. 10 and Fig. 18.14). Init.bit 13: Inverse Checker bit gives the possibility to force all outputs segments in inverse checked form (see Fig. 10 and Fig. 18.15). Init.bit 14: Col bit configures the EM6124 on row and column driver or column driver only. In this mode the frame frequency must be external. Init.bit 15: Row inversion, possibility to inverse the order of the row outputs (see Table 10 and Fig. 18.12). Init.bit 16: M/LSB, possibility to inverse the order loading for RAM data (see Fig. 4). Init.bit 17: Video bit, possibility to inverse the content of the RAM. All the 0L pass to 1L and all the 1L pass to 0L (see Fig. 18.11). Init.bit 18-23: VLCD 64 steps programmation bits. See Fig. 8. Bit 18 (step 1) for MSB and bit 23 (step 6) for LSB. Init.bit 24: Icon bit adds one line more to the selected mux mode ratio for icon segments outputs. Init.bit 25: Sleep 2. Set all outputs at VSS. Init.bit 26-31: Must be setted to 0L.
Command byte only mode
To validate this mode, 8 bits must be shifted with bit 3 to bit 7 setted to 1L. This mode is used for blank, set or sleep mode functions.
Command byte and initialization mode
To validate this mode, 32 bits must be shifted with bit 0 and bit 1 setted to 1L. Bit 2 (sleep) can be active or inactive. Bit 3 to bit 7 (RAM address) can be in any state but it is important that they are not all simultaneously setted to 1L, otherwise the chip will be in command byte only mode.
Command byte and display information mode
To validate this mode, 128 bits must be shifted, eight first bits are for command byte, all the other are RAM data depending of col bit mode and multiplex ratio. There are also x bits don't care in each loading depending on the programmation of the chip (see Fig. 4 for more details). In each RAM's data loading, the command byte has to be introduced for the RAM address. Before loading any data into the RAM the chip has to be initialized.
Command Byte
Commmand Bits 0 to 7 0 Blank 1 Set 2 Sleep 3 4 5 6 RAM address 7
Reset 1
Power-up: Must be followed by a RESET cycle. After the reset 1 pulse the LCD controller driver is set to the following status: - All outputs at VSS - Blank & Set (cmdbits 0,1) = 0L - Sleep mode (cmdbit 2) = 0L - RAM address (cmdbits 3 to 7) = 0L - Multiplex ratio (init.bits 8, 9) = 0L - Temperature coefficient (init.bits 10,11) = 0L - Checker & Inv.Checker (init.bits 12, 13) = 0L - Col Mode (init.bit 14) = 1L - Inv. Row (init.bit 15) = 0L - M/LSB (init.bit 16) = 1L - Video (init.bit 17) = 1L - VLCD step (init.bits 18 to 23) = 0L - Icon (init.bit 24) = 0L - Sleep 2 (init.bit 25) = 1L - The content of the RAM remains unchanged An initialization should take place after reset (32 bits sent).
Table 6
Cmdbit 0: Blank bit forces all column outputs off. Cmdbit 1: Set bit forces all column output on. Note: If bit 0 and bit 1 are both to 1L, the chip will be in initialization mode. See remarks below. Cmdbit 2: Sleep mode bit, stops the voltage booster and the internal oscillator, active bit col forces all outputs to VSS. Cmdbits 3-7: RAM address bits. See table 6. If Cmdbits 3-7 are set to 1L, EM6124 is in Cmd byte only mode.
Initialization Bits
Initialization Bits 8 to 15 8 9 10 11 12 13 14 Col 22 15 Inv.Row 23 Mux Mode Temp. Coeff. Checker Inv.Checker Initialization Bits 16 to 23 16 17 18 19 20 21 M/LSB Video 24 Icon 25 Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Initialization Bits 24 to 31 26 27 Test 5 28 Test 4 29 Test 3 30 Test 2 31 Test 1 Sleep 2 Test 6
Pin Assignment
Name
S1...S121 FR DI DO CLK RES1 RES2 VLCD VDD1 VDD2 VHV VSS
Function
LCD outputs, see Fig.4 AC I/O signal for LCD driver output Serial data input Serial data output Data clock input General reset Reset the serial interface counter Internal generated voltage output Power supply for logic Power supply for analogic Power supply for high voltage Supply GND Table 9
Table 7
Mux ratio (Init. bit 8, 9)
8 0 0 1 1 9 0 1 0 1
mux mode
8 16 20 24
Table 8
4
EM6124
Data Transfer Cycle
Fig. 4
5
EM6124
Output Row Assignments
Mux Mode Row RAM Address Mux 8 Inv. Row 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 S1 S2 S3 S4 S13 S14 S15 S16 1 S16 S15 S14 S13 S4 S3 S2 S1 Mux 8 + Icon Inv. Row 0 S1 S2 S3 S4 S13 S14 S15 S16 S17 1 S17 S16 S15 S14 S13 S4 S3 S2 S1 Mux 16 Inv. Row 0 S1 S2 S3 S4 S5 S6 S7 S8 S13 S14 S15 S16 S17 S18 S19 S20 1 S20 S19 S18 S17 S16 S15 S14 S13 S8 S7 S6 S5 S4 S3 S2 S1 Mux 16 + Icon Inv. Row 0 S1 S2 S3 S4 S5 S6 S7 S8 S13 S14 S15 S16 S17 S18 S19 S20 S21 1 S21 S20 S19 S18 S17 S16 S15 S14 S13 S8 S7 S6 S5 S4 S3 S2 S1 Mux 20 Inv. Row 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 1 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Mux 20 + Icon Inv. Row 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 1 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Mux 24 Inv. Row 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 1 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Mux 24 + Icon Inv. Row 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 1 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1
Table 10
Command Byte Only Mode
time
In this mode only 8 bits have to be shifted into the EM6124 with address bits to logic 1.
Fig. 5
Command Byte and Initialization Mode
time
In this mode only 32 bits have to be shifted into the EM6124 with bits BLANK and SET to logic 1.
Fig. 6 Command Byte and Display Information Mode
time
This mode needs 128 bits shifted into the EM6124. Do not introduce one of the two codes which were described above. (All address bits to logic 1 or BLANK and SET bits to 1 simultaneously)
Fig.7 6
EM6124
Typical VLCD Programming Checker and Checker Inverse
A fast check display can be easily created setting initialization bits 12 and 13 (called "Checker" and "Inv. Checker"). The display is completely checked with only 2 initialization sequences, one "Checker" and one "Inv. Checker". For Checker, the pattern fills the display with alternately ON and OFF pixels as shown in Fig. 10. For Inv. Checker, everything is inverted (see Fig.18.14 and 18.15).
Pattern of Checker Mode
Fig. 10 Internally Generated VLCD versus Temperature Fig. 8 Temperature Control
Due to the temperature dependency of liquid cristals viscosity the LCD controlling voltage VLCD must be increased for lower temperatures to maintain optimal contrast. The EM6124 is available with 4 different temperature coefficients (see Fig. 9). The coefficient is selected by 2 bits in the initialization code TC bits 10 and 11. Table 11 shows the typical values of the different temperature coefficients. They are proportional to the programmed VLCD.
Typical Values of the Temperature Coefficients
Bit 10, Bit 11 00 01 10 11 Value - 0.02 x VLCD - 0.52 x VLCD - 1.16 x VLCD - 1.82 x VLCD Unit mV/C mV/C mV/C mV/C Table 11 Fig. 11
Temperature Coefficients
Fig. 9 7
EM6124
Display Functions
Bit
Logic 0 8 - 9: Mux Mode 10 -11:Temp.Coeff. 12: Checker 13: Inv. Checker 14: Col 15: Inv. Row See table 8 See table 11 Inactive Inactive Colum driver only Increment rows (example for mux 24: row 1, 2, 3, ... , 24, 1, 2, ...) Loading in LSB mode Inverse content of RAM Inactive Inactive Chess display Inverse chess display Row and column driver Decrement rows (example for mux 24: row 24, 23, 22, ... ,2 ,1, 24, 23, ...) Loading in MSB mode Inactive See Fig. 8 Add one line more to seledted mux mode All outputs at VSS Must be at 0L Table 12
State
Logic 1
16: M/LSB 17: Video 18 - 23: VLCD step 24: Icon 25: Sleep 26 - 31:
8
EM6124
Block Diagram
Fig. 12
9
EM6124
LCD Voltage Bias Levels
LCD Drive Type LCD Bias Configuration VOP VOFF (rms) VON (rms) VOFF (rms)
EM6124 (24)
EM6124 (20)
EM6124 (16)
1/5 Bias 6 Levels
EM6124 (8)
1/4 Bias 5 Levels
Table 13
Optimum LCD Bias Voltages
Multiplex Rate 1 : 24 1 : 20 1 : 16 1:8 1 1 1 1 0.830 0.817 0.800 0.750 0.660 0.634 0.600 0.500 0.340 0.366 0.400 0.250 0.170 0.183 0.200 0 0 0 0 VLCD V1 V2 V3 V4 VSS
VLCD > V1 > V2 > V3 > V4 >VSS
The values in the above table are given in reference to VLCD e.g. 0.5 means 0.5 x VLCD
Table 14
10
EM6124
Row and Column Multiplexing Waveform EM6124 (8)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 13
11
EM6124
Row and Column Multiplexing Waveform EM6124 (16)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 14
12
EM6124
Row and Column Multiplexing Waveform EM6124 (20)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 15
13
EM6124
Row and Column Multiplexing Waveform EM6124 (24)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 16
14
EM6124
Functional Description
Supply Voltage VDD1, VDD2, VHV, VLCD, VSS
The voltage between VDD1 and VSS is the supply voltage for the logic and the interface. The voltage between VDD2 and VSS is the supply voltage for the analogic. VDD1 and VDD2 must be the same voltage and, in order to guarantee the best functioning, VDD1 and VDD2 have to be separately connected to the PCB (see Fig. 19). The voltage VLCD is internally generated for the supply voltage of the LCD and is used for the generation of the internal LCD bias level. An external capacitor of 1 F must be connected between VLCD and VSS. Table 15 shows the relationship between V1, V2, V3, V4 for a programmed multiplex rate. Note that VLCD > V1 > V2 > V3 > VSS for the EM6124 8 mux programmed, and for the EM6124 16, 20, 24 mux programmed VLCD > V1 > V2 > V3 > V4 > VSS. The voltage between VHV and VSS is the supply voltage for high voltage part of the EM6124. An external VLCD may also be used by connecting a power supply and programming a lower VLCD voltage during initialization. new loading of data. This reset 2 does not change the content of the RAM neither the content of the command and the initialization bits. To avoid trouble in case of software interrupt of the MPU during data loading, this function can be used.
Power-Up
On power up the data in the shift registers, the display RAM, the sequencer driving the 8/16/20/24 rows and the 121 bit display latches are undefined.
CLK Input
The clock input is used to clock the DI serial data into the EM6124.
FR Input / Output
The frame frequency is realized by an internal oscillator with a typical value of 75 Hz. The internal row frequency changes with the number of rows ( Frow = 75 x n, where n = 8, 16, 20, 24). When bit 14 (Col) is inactive (active low), the frame frequency is given by the internal oscillator. This frequency can be measured on the I/O FR. When bit 14 (Col) is active (active low), the frame frequency is external then the frequency is given directly by the FR input to the row and column driver (see Fig. 16 and 17 for more details concerning the frame frequency).
Data Input
The data input pin, DI, is used to load serial data into the EM6124. The normal serial data word length is128 bits. 32 and 8 bits are also available in a special mode (see 1 Bit Interface Description). The command byte is loaded first and then the segment data bits (see Fig. 4).
Driver Outputs S1 to S116
There are 121 LCD driver outputs on the EM6124. The output assignments depend on the chosen mux mode ratio (init. bits 8, 9) and the Col function (init. bit 14). When init. bit 14 (Col) is active, all 116 outputs function as column drivers. Table "Output Row Assignments" and Fig. 4 describe exactly the correspondent data to the output of the chip. There is one to one relationship between the display RAM and the LCD driver outputs. Each pixel (segment) driven by the EM6124 on the LCD has a display RAM bit which corresponds to it. Setting the bit turns the pixel "on" and Clearing it turns "off".
For chip-on-glass better performances can be obtained by covering the backside of the chip.
RES1 Input
Reset is accomplished by applying an external RES1 pulse (active low). When reset occurs within the specified time, all internal register are reset however the content of the RAM is still unchanged. The state after reset is described on page 4.
RES2 Input
Reset is accomplished by applying an external RES2 pulse (active low). When reset occurs within the specified time, the internal counter for serial interface is reset. The counter of the serial interface for data inputs is ready for a
Typical Frame Frequency at VDD = 3 V
Typical Frame Frequency at TA = 25 C
Fig.17.01
Fig.17.02 15
EM6124
Application Example
These tables/figures show how to use the EM6124 with a given initialization. Rows "Data" show the logical value to affect pad DI for each falling edge of pad CLK. A reset cycle pad RES1 at OL is required before sending data.
Fig. 18.01
Fig. 18.02
Table 15 (continued on next pages)
16
EM6124
Application example continued
Fig. 18.03
Fig. 18.04
Fig. 18.05
17
EM6124
Application example continued
Fig. 18.06
Fig. 18.07
Fig. 18.08
18
EM6124
Application example continued
Fig.18.09
Fig.18.10
Fig.18.11
19
EM6124
Application example continued
Fig. 18.12
Fig. 18.13
Fig. 18.14
20
EM6124
Application example continued
Fig. 18.15
Fig. 18.16
Fig. 18.17
21
EM6124
Applications
Two EM6124 work in parallel to drive up to 50 rows x 96 columns or 25 rows x 212 columns as below
EM6124
EM6124
By connecting the VLCD bias outputs as shown, the pixel load is averaged across all the drivers. The effective bias level source impedance is the parallel combination of the total number of drivers. * VDD1 and VDD2 have been connected together. Fig. 19
Contacting Power Supply
EM6124
In order to guarantee the best functioning VDD1 and VDD2 have to be connected separtely on the PCB, if possible.
Fig. 20
22
EM6124
Dimensions of Chip Form and Bumped Die
All dimensions in micron
Thickness: 15 mils Bump size: LCD output pads = 50 x 100 micron, Input/output pads = 102 x 102 micron Bump height: 17.5 micron Bump hardness: 50 Vickers Chip size: [X x Y] 7930 x 1493 micron or 312 x 59 mils Note: The origin (0,0) is the lower left coordinate of center pads. The lower left corner of the chip shows distances to origin.
Fig. 21
Ordering Information
When ordering, please specify the complete Part Number
Part Number EM6124WP15E Die Form Die in waffle pack, 15 mils thickness Bumping With gold bumps
For other delivery form in die (with or without bumps), please contact EM Microelectronic-Marin S.A. Minimum order quantity might apply.
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
E. & O.E. Printed in Switzerland, Th (c) 2002 EM Microelectronic-Marin SA, 03/02, Vers. D/436
EM Microelectronic-Marin SA, CH-2074 Marin, Switzerland, Tel. +41 - (0)32 75 55 111, Fax +41 - (0)32- 75 55 403 23

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